Are you familiar with VHDL and/or Verilog?
- 1 Answers
- 3684 Views
- Intel, I also Faced
- E-Mail Answers
Answer / sunita
Just like we use Software description languages like C,C++
etc, in the same manner VHDL and Verilog are hardware
Description languages. These languages are used to describe
the hardware that will be used to perform a aprticular
operation.
| Is This Answer Correct ? | 4 Yes | 0 No |
What is component binding?
Insights of a 2 input NAND gate. Explain the working?
How do you size NMOS and PMOS transistors to increase the threshold voltage?
Differences between Signals and Variables in VHDL? If the same code is written using Signals and Variables what does it synthesize to?
You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
Implement D flip-flop with a couple of latches? Write a VHDL Code for a D flip-flop?
What is look up table in vlsi?
Explain sizing of the inverter?
What?s the difference between Testing & Verification?
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
Explain what is the use of defpararm?
Explain CMOS Inverter transfer characteristics?
86 Family 
