Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)

0 Answers   Infosys,

---

What are the different design constraints occur in the synthesis phase?

0 Answers  

---

Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?

13 Answers   Intel,

---

Explain the sizing of the inverter?

1 Answers   Intel,

---

How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?

0 Answers   Infosys,

---

---

For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?

0 Answers   Intel,

---

Draw the Layout of an Inverter?

0 Answers   Intel,

---

Why does the present vlsi circuits use mosfets instead of bjts?

0 Answers  

---

what is the difference between the TTL chips and CMOS chips?

0 Answers  

---

What happens when the gate oxide is very thin?

3 Answers   Intel,

---

What are the limitations in increasing the power supply to reduce delay?

2 Answers   Infosys,

---

What is validation?

2 Answers   Intel,

---