If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?

0 Answers   Intel,

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Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

0 Answers   Infosys,

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Why do we need both PMOS and NMOS transistors to implement a pass gate?

3 Answers   INEL, Intel,

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You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

0 Answers   Infosys,

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Implement a function with both ratioes and domino logic and merits and demerits of each logic?

0 Answers   Intel,

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What is Cross Talk?

4 Answers   Intel,

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Differences between netlist of HSPICE and Spectre?

1 Answers   Intel,

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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.

0 Answers   Infosys,

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6-T XOR gate?

0 Answers   Intel,

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Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers

0 Answers   Infosys,

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Differences between Array and Booth Multipliers?

0 Answers   Intel,

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why is the number of gate inputs to CMOS gates usually limited to four?

0 Answers  

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