What are the different design constraints occur in the synthesis phase?
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What is the ideal input and output resistance of a current source?
Draw the Layout of an Inverter?
You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
What types of high speed CMOS circuits have you designed?
Are you familiar with VHDL and/or Verilog?
What are the different measures that are required to achieve the design for better yield?
What happens when the gate oxide is very thin?
What is the difference between nmos and pmos technologies?
How about voltage source?
what is verilog?
What is Noise Margin? Explain the procedure to determine Noise Margin?