What are the changes that are provided to meet design power targets?

0 Answers  

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How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?

0 Answers   Infosys,

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Implement a function with both ratioes and domino logic and merits and demerits of each logic?

0 Answers   Intel,

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Explain Custom Design Flow?

2 Answers   Intel,

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How do you detect a sequence of "1101" arriving serially from a signal line?

7 Answers   nvidia,

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Explain the Charge Sharing problem while sampling data from a Bus?

0 Answers  

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Give the expression for CMOS switching power dissipation?

2 Answers   Infosys,

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Are you familiar with the term MESI?

1 Answers   Intel,

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what is body effect?

1 Answers  

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Explain sizing of the inverter?

0 Answers   Infosys,

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What are the different design constraints occur in the synthesis phase?

0 Answers  

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How can you model a SRAM at RTL Level?

1 Answers  

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