What is a D-latch? Write the VHDL Code for it?

3 Answers   Intel,

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Are you familiar with the term MESI?

0 Answers   Intel,

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Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can't resize the combinational circuit transistors)

6 Answers  

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Are you familiar with VHDL and/or Verilog?

17 Answers   Intel,

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Insights of a Tri-State Inverter?

3 Answers   Intel,

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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.

0 Answers   Infosys,

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Why do we use a Clock tree?

3 Answers   Intel,

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Differences between blocking and Non-blocking statements in Verilog?

5 Answers   Intel,

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You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

0 Answers   Infosys,

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Differences between DRAM and SRAM?

14 Answers   Infosys, Intel, University, Wipro,

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What is component binding?

2 Answers   Intel,

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Explain Basic Stuff related to Perl?

0 Answers   Intel,

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