Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers


No Answer is Posted For this Question
Be the First to Post Answer

Post New Answer

More VLSI Interview Questions

Draw a 6-T SRAM Cell and explain the Read and Write operations

0 Answers   Infosys,


Explain why present VLSI circuits use MOSFETs instead of BJTs?

0 Answers  


What are the ways to Optimize the Performance of a Difference Amplifier?

0 Answers  


For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

3 Answers   Intel,


In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

0 Answers   Infosys,






What are the steps involved in preventing the metastability?

0 Answers  


Explain Custom Design Flow?

2 Answers   Intel,


What happens if we delay the enabling of Clock signal?

4 Answers  


What is look up table in vlsi?

0 Answers  


You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

0 Answers   Intel,


What are the main issues associated with multiprocessor caches and how might you solve them?

1 Answers   Intel,


Differences between D-Latch and D flip-flop?

17 Answers   AIT, Intel, Sibridge Technologies,


Categories