Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...


Give a circuit to divide frequency of clock cycle by two ?

Answers were Sorted based on User's Feedback



Give a circuit to divide frequency of clock cycle by two ?..

Answer / sravan

take a D Flip Flop. when it is reset output(Q) is zero.
connect the clock which u want to divide to the CP input of
FF. connect Q bar (which is one after the reset)to the D
input of Flip Flop. Take the output from the Q pin of the
Flip Flop, which is divided by two

Is This Answer Correct ?    26 Yes 3 No

Give a circuit to divide frequency of clock cycle by two ?..

Answer / subashini

a T flip flop act as a frequency divider

Is This Answer Correct ?    23 Yes 5 No

Give a circuit to divide frequency of clock cycle by two ?..

Answer / rajanikanth

T FLIP FLOP WILL ACT AS A DEVIDE BY 2 CKT

Is This Answer Correct ?    16 Yes 1 No

Give a circuit to divide frequency of clock cycle by two ?..

Answer / priyanka kokil

any single flip flop itself is a freqency divider circuit

Is This Answer Correct ?    14 Yes 14 No

Give a circuit to divide frequency of clock cycle by two ?..

Answer / harikrishna h

take an xor gate, connect output to one of the input of xor gate and other input as the clock. verilog code for the same is given below
module a(input in,rst,output reg ot);
always @(in or rst)
begin
if(rst)
ot<=0;
else
ot<=ot ^ in;
end
endmodule

Is This Answer Correct ?    0 Yes 2 No

Give a circuit to divide frequency of clock cycle by two ?..

Answer / manish sharma

Divide the clock frequency by 2
A 2:1 MUX with CLK as select signal. The 0 select input is just the output. The 1 select input is output_bar(NOT output).

Is This Answer Correct ?    1 Yes 4 No

Post New Answer

More 86 Family Interview Questions

Explain the internal architecture of the 8086 microprocessor?

0 Answers  


What are the index registers in 8086?

0 Answers  


Define the type of interrupts in the 8085 processor?

0 Answers  


What is general purpose registers in 8086?

0 Answers  


Name 5 different addressing modes?

0 Answers  


What are set up time & hold time constraints?

0 Answers  


List the various registers of 8085?

0 Answers  


What is meant by cross-compiler?

0 Answers  


What is PSW?

11 Answers   DRDO,


What is the purpose of a buffer register in reference to 8085?

0 Answers  


Define bit?

0 Answers  


What are the different types of instructions of 8085?

0 Answers  


Categories