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Give a circuit to divide frequency of clock cycle by two ?
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Answer Posted / harikrishna h
take an xor gate, connect output to one of the input of xor gate and other input as the clock. verilog code for the same is given below
module a(input in,rst,output reg ot);
always @(in or rst)
begin
if(rst)
ot<=0;
else
ot<=ot ^ in;
end
endmodule
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