What are set up time & hold time constraints What do they
signify Which one is critical for estimating maximum clock
frequency of a circuit?
- 1 Answers
- 8861 Views
- AMD, I also Faced
- E-Mail Answers
Answer / vinita jain
Set up time constraint signifies how late the input signal
can arrive before the active edge of the flip-flop. Smaller
the set up time, the better.
Hold time on the other hand signifies how long the value at
the input needs to be held stable after the the active edge.
Again the smaller the hold time, the better.
For estimating maximum clock frequency, set up time is critical.
| Is This Answer Correct ? | 27 Yes | 1 No |
What are the different types of addressing modes?
Mention the types of programmed data transfer?
What all does a microprocessor comprise of?
Explain all the addressing modes of the 8085 with the help of examples.
Describe the non-vectored interrupt process?
What happens during DMA transfer?
What is the maximum size of segment in 8086 microprocessor?
Define the architecture of the 8085 microprocessor?
How clock signal is generated in 8086?
Explain the significance of signal?
What is the difference between harvard architecture and von neumann architecture?
What is system bus?
86 Family 
