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if one of the critical section code (linked list) is under
ISR & another one in kernel thread ? How you will
synchronize for this critical section code ?
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Answer / nt
In the kernel thread you need to disable interrupts before
critical section code starts and then enable interrupts
just after critical section ends. In this way u will make
sure that either ISR or kernel thread execute critical
section at a time.
| Is This Answer Correct ? | 12 Yes | 0 No |
Answer / rulingminds
For this situation in SMP case spinlocks are used
| Is This Answer Correct ? | 3 Yes | 0 No |
Answer / prasad
As per my knowledge disabling interrupts is fine with
single processor environment, but don't work in multi-
processor environment. Another processor may try to update
the critical section code while one processer is serving
the ISR. So in multi-processor environment it requires more
protected mechanism.
| Is This Answer Correct ? | 3 Yes | 1 No |
Answer / suhas
Why cant we have lock mechanism working here. Assign a lock
to the address space pointed to by the data structure.
Something like monitors or semaphores, why wouldn't that
work fine...instead of disabling interrupts and stuff...
| Is This Answer Correct ? | 1 Yes | 5 No |
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