if one of the critical section code (linked list) is under
ISR & another one in kernel thread ? How you will
synchronize for this critical section code ?
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Answer Posted / prasad
As per my knowledge disabling interrupts is fine with
single processor environment, but don't work in multi-
processor environment. Another processor may try to update
the critical section code while one processer is serving
the ISR. So in multi-processor environment it requires more
protected mechanism.
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