Basic Stuff related to Perl?

0 Answers   Intel,

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Explain what is slack?

0 Answers  

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What is the difference between synchronous and asynchronous reset?

0 Answers  

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Advantages and disadvantages of Mealy and Moore?

2 Answers   Intel,

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WHAT IS THE DIFFERENCE BETWEEN TESTING AND VERIFICATION OF VLSI CIRCUIT?

5 Answers   Intel, Wipro,

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What are the main issues associated with multiprocessor caches and how might you solve them?

1 Answers   Intel,

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What happens to delay if you increase load capacitance?

3 Answers   Infosys,

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Mention what are the different gates where Boolean logic are applicable?

0 Answers  

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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Explain the working of Insights of an inverter ?

0 Answers   Intel,

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Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram

0 Answers   Infosys,

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Give the cross-sectional diagram of the cmos.

0 Answers  

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