Suppose you have a combinational circuit between two
registers driven by a clock. What will you do if the delay
of the combinational circuit is greater than your clock signal?
Answers were Sorted based on User's Feedback
Answer / ravi desai
Put even number of not gates between clocks of reg A and
Reg B. The not gates will introduce delay between clock of
reg A and reg B.
| Is This Answer Correct ? | 5 Yes | 2 No |
Answer / priyesh
If the circuit given is asynchronous then we can lower the
delay by supplying the same clock to all flip flops i.e.
making the circuit synchronous.
Another way is by adding NOT gates between clock and register
| Is This Answer Correct ? | 0 Yes | 0 No |
Answer / ravi desai
put even number not gates between clock of reg A and Reg B.
the not gates will introduce delay.
| Is This Answer Correct ? | 2 Yes | 4 No |
Which bit of the flag register is set when output overflows to the sign bit?
State the differences between absolute and linear select decosing.
What is the purpose of pipe lining in reference to 8086?
Explain the purpose of the status register?
Define bit?
What is the purpose of Program Counter in a Micro - Processor?
Give a circuit to divide frequency of clock cycle by two ?
What is the the total addressable memory size in a 8085 microprocessor?
State the order of interrupts priority wise (lower to higher)?
what is logical address?
How do vectored and non-vectored interrupts differ?
What is the bhe signal?