What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

0 Answers   Intel,

---

Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

0 Answers   Infosys,

---

What is clock feed through?

2 Answers   Intel,

---

what are three regions of operation of MOSFET and how are they used?

0 Answers  

---

what is short Channel effect.

2 Answers  

---

What are the total number of lines written by you in C/C++? What compiler was used?

1 Answers   Intel, Zensar,

---

Explain the difference between write through and write back cache.

2 Answers   Intel,

---

Give the expression for CMOS switching power dissipation?

2 Answers   Infosys,

---

Explain about stuck at fault models, scan design, BIST and IDDQ testing?

3 Answers   Intel,

---

Implement F = AB+C using CMOS gates?

2 Answers   Intel,

---

What is Cross Talk?

4 Answers   Intel,

---

Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

4 Answers   Intel,

---