Answer / chaitanya

SETUP time : Minimum time the data should be stable before
the arrival of clock edge

HOLD time : Minum time data shuold be stable after the
arrival of clock edge.

Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

0 Answers   Infosys,

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What is the purpose of having depletion mode device?

0 Answers  

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What happens to delay if you increase load capacitance?

3 Answers   Infosys,

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Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?

13 Answers   Intel,

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What is the difference between nmos and pmos technologies?

0 Answers  

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What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

0 Answers   Intel,

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Why is OOPS called OOPS? (C++)

1 Answers   ARM, Intel,

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What is the mealy and moore machine's state diagram that can detect 3 consecutive heads of 3 coins ?

2 Answers  

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Why is Extraction performed?

1 Answers   Intel,

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What types of high speed CMOS circuits have you designed?

2 Answers   Infosys, Intel,

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Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

0 Answers   Infosys,

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You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

0 Answers   Infosys,

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