Answer / geo

program status word.... a reg in the
microcontroller/microprocessor s showing the current current
status of alu operation

eg: if a carry is generated after an alu operation ,the
corresponding carry flag bit in this reg will set 1.

like if the result is a zero, then the zero flag is set...

Answer / pratik

5 bits indicate the 5 status flags and 3 bits are
undefined. The combination of these 8 bits is called
Program status Word(PSW). PSW and the accumulator are
treated as a 16 bit stack pointer

Answer / saravanan

PSW is program status word. it contains various flags like
sign, zero, carry, auxillary carry, and parity . these
flags are affected by result of ALU.

Answer / mahim nimbawat

PSW stands for Program Status Word, it is 16-bits hardware
register that maintains the status of program being
executed. It shows the current status of ALU operation.
[psw]<- [A]+[flag]

Answer / santhoshi

The Program Status Word (PSW) contains status bits that
reflect the current CPU state

Answer / noor

PSW stands for Program Status Word, it is 16-bits hardware
register that maintains the status of program being
executed. It shows the current status of ALU operation.

Answer / md riyaz alam

program status word.... a reg in the
microcontroller/microprocessor s showing the current current
status of alu operation

eg: if a carry is generated after an alu operation ,the
corresponding carry flag bit in this reg will set 1.

like if the result is a zero, then the zero flag is set...

Answer / hamza khan

Outcome of the last arithmetic operation (zero,-ve, +ve, overflow, carry)

Answer / nandhini. r

PSW is a 8-bit register. 5 bit indicates status of 5 flags.
3 bits are user definable.

Answer / dhananjay mishra

In computer ,the program status word is an area of memory or a hardware register which contains information about program stateused by the operating system and the underlying hardware.It will normally include a pointer(address)to the next instruction to be executed.

Give a circuit to divide frequency of clock cycle by two ?

6 Answers  

I have code and test bench however it is not working porperly. Need help to get it working. module fsm(clock,reset,coin,vend,state,change); \\these are the inputs and the outputs. input clock; input reset; input [2:0]coin; output vend; output [2:0]state; output [2:0]change; \\i need to define the registers as change,coin and vend reg vend; reg [2:0]change; wire [2:0]coin; \\my coins are declared as parameters to make reading better. parameter [2:0]NICKEL=3’b001; parameter [2:0]DIME=3’b010; parameter [2:0]NICKEL_DIME=3’b011; parameter [2:0]DIME_DIME=3’b100; parameter [2:0]QUARTER=3’b101; \\MY STATES ARE ALSO PARAMETERS . I DONT WANT TO MAKE YOU READ \\IN MACHINE LANGUAGE parameter [2:0]IDLE=3’b000; parameter [2:0]FIVE=3’b001; parameter [2:0]TEN=3’b010; parameter [2:0]FIFTEEN=3’b011; parameter [2:0]TWENTY=3’b100; parameter [2:0]TWENTYFIVE=3’b101; \\AS ALWAYS THE STATES ARE DEFINED AS REG reg [2:0]state,next_state; \\MY MACHINE WORKS ON STATE AND COIN always @(state or coin) begin next_state=0; \\VERYFIRST NEXT STATE IS GIVEN ZERO case(state) IDLE: case(coin) \\THIS IS THE IDLE STATE NICKEL: next_state=FIVE; DIME: next_state=TEN; QUARTER: next_state=TWENTYFIVE; default: next_state=IDLE; endcase FIVE: case(coin) \\THIS IS THE SECOND STATE NICKEL: next_state=TEN; DIME: next_state=FIFTEEN; QUARTER: next_state=TWENTYFIVE; //change=NICKEL default: next_state=FIVE; endcase TEN: case(coin) \\THIS IS THE THIRD STATE NICKEL: next_state=FIFTEEN; DIME: next_state=TWENTY; QUARTER: next_state=TWENTYFIVE; //change=DIME default: next_state=TEN; endcase FIFTEEN: case(coin) \\THIS IS THE FOURTH STATE NICKEL: next_state=TWENTY; DIME: next_state=TWENTYFIVE; QUARTER: next_state=TWENTYFIVE; //change==NICKEL_DIME default: next_state=FIFTEEN; endcase TWENTY: case(coin) \\THIS IS THE FIFTH STATE NICKEL: next_state=TWENTYFIVE; DIME: next_state=TWENTYFIVE; //change=NICKEL QUARTER: next_state=TWENTYFIVE; //change==DIME_DIME default: next_state=TWENTY; endcase TWENTYFIVE: next_state=IDLE; \\THE NEXT STATE HERE IS THE RESET default : next_state=IDLE; endcase end always @(clock) begin \\WHENEVER I GIVE A RESET I HAVE TO MAKE THE STATE TO IDLE AND VEND TO 1 if(reset) begin state <= IDLE; vend <= 1’b0; // change <= 3’b000; end \\THE CHANGE ALSO HAS TO BECOME NONE else state <= next_state; case (state) \\HERE WE DECIDE THE NEXT STATE \\ALL THE STATES ARE DEFINED HERE AND THE OUTPUT IS ALSO GIVEN IDLE: begin vend <= 1’b0; change <=3’d0; end FIVE: begin vend <= 1’b0; if (coin==QUARTER) change <=NICKEL; else change <=3’d0; TEN: begin vend <= 1’b0; if (coin==QUARTER) change <=DIME; else change <= 3’d0; FIFTEEN : begin vend <= 1’b0; if (coin==QUARTER) change <=NICKEL_DIME; else change TWENTY : begin vend <= 1’b0; if (coin==DIME) change <=NICKEL; else if (coin==QUARTER) TWENTYFIVE : begin vend <= 1’b1; change <=3’d0; end default: state <= IDLE; endcase end endmodule module test; \\THE INPUT IN THE FSM MODULE ARE REG HERE reg clock,reset; reg [2:0]coin; \\THE OUTPUT IN THE FSM MODULE ARE WIRES HERE wire vend; wire [2:0]state; wire [2:0]change; \\THE PARAMETERS AGAIN FOR THE COIN AND STATE parameter [2:0]IDLE=3’b000; parameter [2:0]FIVE=3’b001; parameter [2:0]TEN=3’b010; parameter [2:0]FIFTEEN=3’b011; parameter [2:0]TWENTY=3’b100; parameter [2:0]TWENTYFIVE=3’b101; parameter [2:0]NICKEL=3’b001; parameter [2:0]DIME=3’b010; parameter [2:0]NICKEL_DIME=3’b011; parameter [2:0]DIME_DIME=3’b100; parameter [2:0]QUARTER=3’b101; \\I MONITOR THE TIME,DRINK,RESET,CLOCK,STATE AND CHANGE FOR CHANGES. initial begin $display("Time\tcoin\tdrink\treset\tclock\tstate\tchange"); $monitor("%g\t%b\t%b\t%b\t%b\t%d\t% d",$time,coin,vend,reset,clock,state,change); \\NEW FEATURE: MY MACHINE HAS THE FACILITY TO DUMP VARIABLES SO THAT \\ I CAN VIEW THEM USING A VCD VIEWER. $dumpvars; $dumpfile("file.vcd"); // Dump output file. \\THIS IS WHERE THE COINS ARE ADDED. clock=0; reset=1; \\FIRST LETS RESET THE MACHINE #2 reset=0; coin=NICKEL; \\CHECK FOR STATE 1 #2 reset=1; coin=2’b00; #2 reset=0; coin=DIME; \\RESET AGAIN AND CHECK FOR STATE 2 #2 reset=1; coin=2’b00; #2 reset=0; \\RESET AGAIN AND CHECK FOR STATE 5 coin=QUARTER; #2 reset=1; coin=2’b00; #2 reset=0; \\RESET AGAIN AND CHECK FOR STATE 5 coin=NICKEL; #2 coin=NICKEL; #2 coin=NICKEL; #2 coin=NICKEL; #2 coin=NICKEL; #2 reset=1; coin=2’b00; #2 reset=0; \\RESET AGAIN AND CHECK FOR STATE 5 AND SO ON coin=NICKEL; #2 coin=DIME; #2 coin=DIME; #2 reset=1; coin=2’b00; #2 reset=0; coin=NICKEL; #2 coin=DIME; #2 coin=QUARTER; #2 reset=1; coin=2’b00; #2 reset=0; coin=NICKEL; #2 coin=NICKEL; #2 coin=NICKEL; #2 coin=DIME; #2 reset=1; coin=2’b00; #2 reset=0; coin=NICKEL; #2 coin=NICKEL; #2 coin=NICKEL; #2 coin=NICKEL; #2 coin=DIME; #2 reset=1; coin=2’b00; #2 reset=0; coin=NICKEL; #2 coin=NICKEL; #2 coin=QUARTER; #2 reset=1; coin=2’b00; #2 reset=0; coin=NICKEL; #2 coin=QUARTER; #2 reset=1; coin=2’b00; #2 $finish; end \\THE CLOCK NEEDS TO TICK EVERY 2 TIME UNIT always #1 clock=~clock; //always @(state) // coin=!coin; initial begin if (reset) coin=2’b00; end \\THIS IS WHERE I INSTANTIATE THE MACHINE fsm inst1(clock,reset,coin,vend,state,change); endmodule

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