What are the different design constraints occur in the synthesis phase?

0 Answers  

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Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can't resize the combinational circuit transistors)

6 Answers  

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A circuit has 1 input X and 2 outputs A and B. If X = HIGH for 4 clock ticks, A = 1. If X = LOW for 4 clock ticks, B = 1. Draw a state diagram for this Spec?

3 Answers   Intel,

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Implement an Inverter using a single transistor?

4 Answers   Intel,

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Implement F= not (AB+CD) using CMOS gates?

0 Answers   Intel,

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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.

0 Answers   Infosys,

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Insights of a 2 input NAND gate. Explain the working?

1 Answers   Intel,

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Cross section of a PMOS transistor?

0 Answers   Intel,

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Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

0 Answers   Infosys,

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Insights of a pass gate. Explain the working?

0 Answers   Intel,

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For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

0 Answers   Infosys,

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What is the build-in potential?

1 Answers   Wipro,

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