Answer / suresh

clock skew,positive skew,negative skew

In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

1 Answers   Intel,

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What transistor level design tools are you proficient with? What types of designs were they used on?

0 Answers   Intel,

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For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

0 Answers   Infosys,

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Tell me how BJT works.

2 Answers  

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What are set up time & hold time constraints? What do they signify?

3 Answers  

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How does Resistance of the metal lines vary with increasing thickness and increasing length?

3 Answers   Infosys,

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Explain the operation considering a two processor computer system with a cache for each processor.

0 Answers   Intel,

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Explain Custom Design Flow?

2 Answers   Intel,

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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.

0 Answers   Infosys,

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In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

0 Answers   Infosys,

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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.

0 Answers   Infosys,

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Explain how logical gates are controlled by Boolean logic?

0 Answers  

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