What is a D-latch? Write the VHDL Code for it?
- 3 Answers
- 21106 Views
- Intel, I also Faced
- E-Mail Answers
Answer Posted / sghsg
library ieee;
use ieee.std_logic_1164.all;
entity D_latch is
port (
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end D_latch;
architecture arch_D_latch of D_latch is
begin
process(d,clk)
begin
-- +ve level sensitive
if(clk = '1') then
q <= d;
else
q <= q;
end if;
end process;
end arch_D_latch;
| Is This Answer Correct ? | 0 Yes | 0 No |
Post New Answer View All Answers
What types of CMOS memories have you designed? What were their size? Speed?
What is the difference between synchronous and asynchronous reset?
Mention what are the different gates where Boolean logic are applicable?
You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
what is verilog?
What is the difference between the mealy and moore state machine?
what is Slack?
Working of a 2-stage OPAMP?
What is Body Effect?
Are you familiar with the term snooping?
For CMOS logic, give the various techniques you know to minimize power consumption
Explain the Various steps in Synthesis?
How about voltage source?
What is the ideal input and output resistance of a current source?
