Answer Posted / purna
The main goals of CTS are
1. Clock signal is propagate to all flops in same time.
2. Low global and local skew.
3. Less insertion delay.
4. For low power designs Clock gating cells are added based
on the designer requirement.
5.Selecting a tree structure from (H,Y,binary and fish bone
etc...)
6. less number of buffer and inverters in the clock path.
7. Clock pin has high fanout to balance skew, we need to
synthesis the clock path separately.
Is This Answer Correct ? | 3 Yes | 0 No |
Post New Answer View All Answers
For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?
What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus
Draw the stick diagram of a NOR gate. Optimize it
Explain the Charge Sharing problem while sampling data from a Bus?
Explain various adders and difference between them?
Explain the operation considering a two processor computer system with a cache for each processor.
what is the difference between the TTL chips and CMOS chips?
What are the different ways in which antenna violation can be prevented?
How to improve these parameters? (Cascode topology, use long channel transistors)
Explain the working of Insights of an inverter ?
What transistor level design tools are you proficient with? What types of designs were they used on?
For CMOS logic, give the various techniques you know to minimize power consumption
What transistor level design tools are you proficient with? What types of designs were they used on?
Explain about 6-T XOR gate?
For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)