Suppose you have a combinational circuit between two
registers driven by a clock. What will you do if the delay
of the combinational circuit is greater than your clock
signal? (You can't resize the combinational circuit
transistors)
Answer Posted / pavankumar v vijapur
use register retiming concept .......
i.e split up comb delay in two paths using a flop
Is This Answer Correct ? | 4 Yes | 1 No |
Post New Answer View All Answers
Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
How does Vbe and Ic change with temperature?
What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?
Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
Explain the Various steps in Synthesis?
What is the function of chain reordering?
For CMOS logic, give the various techniques you know to minimize power consumption
Give the cross-sectional diagram of the cmos.
Explain sizing of the inverter?
Explain what is the use of defpararm?
Design an 8 is to 3 encoder using 4 is to encoder?
How to improve these parameters? (Cascode topology, use long channel transistors)
For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)