Suppose you have a combinational circuit between two
registers driven by a clock. What will you do if the delay
of the combinational circuit is greater than your clock signal?
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Answer / ravi desai
Put even number of not gates between clocks of reg A and
Reg B. The not gates will introduce delay between clock of
reg A and reg B.
| Is This Answer Correct ? | 5 Yes | 2 No |
Answer / priyesh
If the circuit given is asynchronous then we can lower the
delay by supplying the same clock to all flip flops i.e.
making the circuit synchronous.
Another way is by adding NOT gates between clock and register
| Is This Answer Correct ? | 0 Yes | 0 No |
Answer / ravi desai
put even number not gates between clock of reg A and Reg B.
the not gates will introduce delay.
| Is This Answer Correct ? | 2 Yes | 4 No |
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