What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
2734What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
1 4286Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
2631What transistor level design tools are you proficient with? What types of designs were they used on?
4562If not into production, how far did you follow the design and why did not you see it into production?
1 4552What are set up time & hold time constraints What do they signify Which one is critical for estimating maximum clock frequency of a circuit?
AMD,
1 8857
List out some of the commonly found errors in Embedded Systems?
What is your experience with technical documentation?
What is lookup table microcontroller?
What is the purpose of having depletion mode device?
What's the price in 1K quantity?
What is null pointer and what is its use?
What type of scheduling is there in rtos?
What is a 'const' variable?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
What is loop unrolling?
Describe the aaa instruction with the help of an example?
What are the different types of instructions of 8085?
In Verilog code what does “timescale 1 ns/ 1 ps” signifies?
What are different adder circuits you studied?
What is the maximum internal clock frequency of 8086?