Answer Posted / bhyreshkj
By applying the gate voltage we can create a channel b/w source and drain. thereafter by increasing the Vds, the current Id flow from source to drain. Depending upon gate voltage Vg we can manipulate the width of the channel b/w Source and Drain. it will reflect on Id current variation.
| Is This Answer Correct ? | 0 Yes | 0 No |
Post New Answer View All Answers
How do you size NMOS and PMOS transistors to increase the threshold voltage?
Explain what is scr (silicon controlled rectifier)?
What is the function of tie-high and tie-low cells?
Mention what are three regions of operation of mosfet and how are they used?
Explain the three regions of operation of a mosfet.
Draw the stick diagram of a NOR gate. Optimize it
What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
What is Noise Margin? Explain the procedure to determine Noise Margin?
Explain various adders and difference between them?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
What are the steps required to solve setup and hold violations in vlsi?
Mention what are the two types of procedural blocks in Verilog?
Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?