Answer Posted / venkatesh

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

1583

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Working of a 2-stage OPAMP?

3171

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Implement a function with both ratioed and domino logic and merits and demerits of each logic?

3772

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what is the difference between the TTL chips and CMOS chips?

1108

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What are the steps involved in designing an optimal pad ring?

1155

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What's the price in 1K quantity?

2811

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What are the main issues associated with multiprocessor caches and how might you solve them?

2210

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what are three regions of operation of MOSFET and how are they used?

1221

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What is the critical path in a SRAM?

3180

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Draw the stick diagram of a NOR gate. Optimize it

1266

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What is the function of chain reordering?

1050

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Tell me how MOSFET works.

2410

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what is Slack?

1168

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3856

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What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

1314

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