Draw a 6-T SRAM Cell and explain the Read and Write operations
Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
Draw a CMOS Inverter. Explain its transfer characteristics
How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?
For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
For CMOS logic, give the various techniques you know to minimize power consumption
What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus
Draw the SRAM Write Circuitry
Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.
Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
