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For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?
Implement a function with both ratioes and domino logic and merits and demerits of each logic?
Explain the working of Insights of a pass gate ?
Explain the Working of a 2-stage OPAMP?
Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.
Draw the stick diagram of a NOR gate. Optimize it
Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.
Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
Draw a 6-T SRAM Cell and explain the Read and Write operations
Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
