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Answer / prajosh premdas
"IRQ is serviced at a normal priority level and FIQ is
serviced at high priority level." This statement is wrong
FIQ is the fast interrupt i.e. the latency time taken is less because in the FIQ mode (in case of ARM architecture where these modes are encountered) the mode has an additional set of 8 general purpose registers which means in case of the banked registers there is no need to store these registers into stack when the interrupt occurs.
That means r0 to r7 only needs to be stored while moving from User mode to FIQ mode whereas while moving from to IRQ mode r0 to r12 needs to be stored.
|Is This Answer Correct ?||29 Yes||3 No|
Answer / ravi a joshi
I hope you wished to know the difference between IRQ and
FIQ. If so, here goes the answer:
CPU is a sequentially executing machine. It will execute the
instructions from it's instruction set one-by-one until
either program execution sequence is modified or the CPU is
instructed to stop execution.
However, if any peripheral device wishes the CPU to know
that it needs it's attention, then they inform through
interrupts. IRQ stands for Interrupt Request and FIQ stands
for Fast Interrupt Request.
IRQ is serviced at a normal priority level and FIQ is
serviced at high priority level.
|Is This Answer Correct ?||35 Yes||11 No|
Answer / thiagarajan
1.FIQ has the priority level 3 whereas IRQ has the priority
2.FIQ will not be disabled in IRQ handler by default but
IRQ will be diasbled in FIQ handler.
3.IRQ vector presents at the address 0x00000018 where the
FIQ vector presents at the address 0x0000001C which is last
of the vector table. So if IRQ occurs, the handler at
0x00000018 should use a branch instruction to redirect to
service routine. But in FIQ,(as it is the last in vector
table) the service routine can start at the 0x0000001C
itself. One branch instruction processing time will be
saved in FIQ comparing to IRQ.
4.As already mentioned in other answer, FIQ mode has 5
extra general purpose banked register.So there is less
burden in storing the corresponding registers in other mode
to stack while entering FIQ and from stack to registers
while returning from FIQ.
In short FIQ has short interrupt latency(response) than
|Is This Answer Correct ?||13 Yes||1 No|
Answer / mujeer
FIQ has higher priority then IRQ.
As said above it has the 8 banked register to reduce context
switching which improves interrupt latency.
|Is This Answer Correct ?||7 Yes||3 No|
I have been working on one thread which manage and control a couple of circular buffers. It has api for other thread to access. As the thread grows bigger and bigger, I split it as 3 to 4 threads which need to share common buffers, and also their api could be used by other threads, (not these three threads). Inside api, I also allow other threads to access these three threads' common buffers(more than one buffer). SO I have to use mutex to avoid race condition . But I found mutex will be everwhere in all the threads when they update the common buffer. I am wondering whether I could reduce mutex usage(more mutex will hure my system performance). any ideas for how to reduce mutex usage meanwhile to avoid race condition. Thanks
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