Design a timer circuit using VHDL which has the following:
input : start_timer(ST) output: long_time(LT) short_time(ST)
when the timer is triggered by the ST(either 0 or 1) signal
the timer should generate two timing signals
accordingly.While the long time is going ON the other should
be OFF and vice versa.
Answer / Amit Kumar Jayant
Here's a simple VHDL code for your requirement: nn```vhdlnentity timer isn port(n start_timer : in std_logic;n long_time : out std_logic;n short_time : out std_logicn );nend timer;nnarchitecture behavior of timer isnbeginn signal clock, enable : std_logic := '0';n signal count : natural range 0 to 10;nn process(start_timer, clock)n beginn if rising_edge(clock) thenn if start_timer = '1' thenn enable <= not enable;n elsen enable <= '0';n end if;n end if;n end process;nn process(enable)n beginn if enable = '1' thenn if count = 5 thenn long_time <= '1';n short_time <= '0';n count <= 0;n elsif count > 0 thenn count <= count + 1;n end if;n end if;n end process;nn -- Clock generationn processn beginn clock <= not clock after 50 ns;n end process;nend behavior;n```
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