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  • CAT aptitute test questions (11)
  • CAT interview questions (19)
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CAT General Aptitude Interview Questions
Questions Answers Views Company eMail

there is number X in decimal represntation whose last digit is not 0. if digits of X are reversed then we obtain new number say Y. both X and Y are divisible by 7. then find all such X from 10 to 1000.

5 4082

can anyone please tell me the written test pattern for FIDELITY (for incampus)for freshers......

4447

A train X starts from Meerut at 4 p.m and reaches Ghaziabad at 5 p.m while another train Y starts from Ghaziabad at 4 p.m and reaches Meerut at 5:30 p.m? At what time will the trains meet?

18 14250

How many triangles are there in the following figure?

2 7233

Ajay told bharat i am 4 times as old as you were when i was as old as you are.Bharat told ajay 10 years ago i was 9 years younger to you.Find the sum of present ages of Ajay and Bharat.

4 7320





Consider the sequence of numbers a1, a2, a3, ..... to infinity where a1 = 81.33 and a2 = -19 and aj = aj-1 -aj-2 for j ≥ 3. What is the sum of the first 6002 terms of this sequence?

1 3213

The remainder, when (1523 + 2323) is divided by 19, is

3 3953

Let C be a circle with centre P0 and AB be a diameter of C. Suppose P1 is the mid point of the line segment P0B, P2 is the mid point of the line segment P1B and so on. Let C1, C2, C3, ...... be circles with diameters P0P1, P1P2, P2P3 ... respectively. Suppose the circles C1 C2, C3, .... are all shaded. The ratio of the area of the unshaded portion of C to that of the original circle C is

4 7191

find the remainder when 2222^(5555)+5555^(2222)is divided by 7

3 13433

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Un-Answered Questions

difference betwwn 16 bit and 32 bit

991


what is market share??tell me detailed abt it??

820


What support services are available with Windows Server 2003?

1114


Standard mrp steps

718


What is unique about B.L.M business that would impact the future client/server architechture or software needs of your G.I.S programme?

1198






For group 1 , 2 whather i have to prepare my technical or general studies etc? and im graduate in ee engg. for wht posts im eligible for? please tell me!

877


Need to convert this VHDL code into VLSI verilog code? LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ----using all functions of specific package--- ENTITY tollbooth2 IS PORT (Clock,car_s,RE : IN STD_LOGIC; coin_s : IN STD_LOGIC_VECTOR(1 DOWNTO 0); r_light,g_light,alarm : OUT STD_LOGIC); END tollbooth2; ARCHITECTURE Behav OF tollbooth2 IS TYPE state_type IS (NO_CAR,GOTZERO,GOTFIV,GOTTEN,GOTFIF,GOTTWEN,CAR_PAID,CHEATE D); ------GOTZERO = PAID $0.00--------- ------GOTFIV = PAID $0.05---------- ------GOTTEN = PAID $0.10---------- ------GOTFIF = PAID $0.15---------- ------GOTTWEN = PAID $0.20--------- SIGNAL present_state,next_state : state_type; BEGIN -----Next state is identified using present state,car & coin sensors------ PROCESS(present_state,car_s,coin_s) BEGIN CASE present_state IS WHEN NO_CAR => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= NO_CAR; END IF; WHEN GOTZERO => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTZERO; ELSIF (coin_s = "01") THEN next_state <= GOTFIV; ELSIF (coin_s ="10") THEN next_state <= GOTTEN; END IF; WHEN GOTFIV=> IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIV; ELSIF (coin_s = "01") THEN next_state <= GOTTEN; ELSIF (coin_s <= "10") THEN next_state <= GOTFIV; END IF; WHEN GOTTEN => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s ="00") THEN next_state <= GOTTEN; ELSIF (coin_s="01") THEN next_state <= GOTFIV; ELSIF (coin_s="10") THEN next_state <= GOTTWEN; END IF; WHEN GOTFIF => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIF; ELSIF (coin_s ="01") THEN next_state <= GOTTWEN; ELSIF (coin_s = "10") THEN next_state <= GOTTWEN; END IF; WHEN GOTTWEN => next_state <= CAR_PAID; WHEN CAR_PAID => IF (car_s = '0') THEN next_state <= NO_CAR; ELSE next_state<= CAR_PAID; END IF; WHEN CHEATED => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= CHEATED; END IF; END CASE; END PROCESS;-----End of Process 1 -------PROCESS 2 for STATE REGISTER CLOCKING-------- PROCESS(Clock,RE) BEGIN IF RE = '1' THEN present_state <= GOTZERO; ----When the clock changes from low to high,the state of the system ----stored in next_state becomes the present state----- ELSIF Clock'EVENT AND Clock ='1' THEN present_state <= next_state; END IF; END PROCESS;-----End of Process 2------- --------------------------------------------------------- -----Conditional signal assignment statements---------- r_light <= '0' WHEN present_state = CAR_PAID ELSE '1'; g_light <= '1' WHEN present_state = CAR_PAID ELSE '0'; alarm <= '1' WHEN present_state = CHEATED ELSE '0'; END Behav;

3986


Hi Experts could u please me some questions with answers like they will ask in interview for experiences peoples to test whether they are experiences or not? its urgent.

523


how to check earthing,what is minum ohms for proper earthing

810


please give me solution to rectify the emi(electromagnetic interference)

754


How can you tell how much space is left on a given file system and how much space each of the file system's subdirectories take-up?

1349


Sql questions to find second max salary and how to use joins

239


Risk Analysis a) 2 step, b)3 step, c) 4 step, d) 6 step

881


What is c.g.i sheet which used for roof??

539


how can we say that stator magnetic field rotates with synchronous speed?can we derive?

578






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