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ASD Lab Microsoft Certifications Interview Questions
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Peer to Peer Network belong to which topology? a.ring b,bus c Star d None

4 4668

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Need to convert this VHDL code into VLSI verilog code? LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ----using all functions of specific package--- ENTITY tollbooth2 IS PORT (Clock,car_s,RE : IN STD_LOGIC; coin_s : IN STD_LOGIC_VECTOR(1 DOWNTO 0); r_light,g_light,alarm : OUT STD_LOGIC); END tollbooth2; ARCHITECTURE Behav OF tollbooth2 IS TYPE state_type IS (NO_CAR,GOTZERO,GOTFIV,GOTTEN,GOTFIF,GOTTWEN,CAR_PAID,CHEATE D); ------GOTZERO = PAID $0.00--------- ------GOTFIV = PAID $0.05---------- ------GOTTEN = PAID $0.10---------- ------GOTFIF = PAID $0.15---------- ------GOTTWEN = PAID $0.20--------- SIGNAL present_state,next_state : state_type; BEGIN -----Next state is identified using present state,car & coin sensors------ PROCESS(present_state,car_s,coin_s) BEGIN CASE present_state IS WHEN NO_CAR => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= NO_CAR; END IF; WHEN GOTZERO => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTZERO; ELSIF (coin_s = "01") THEN next_state <= GOTFIV; ELSIF (coin_s ="10") THEN next_state <= GOTTEN; END IF; WHEN GOTFIV=> IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIV; ELSIF (coin_s = "01") THEN next_state <= GOTTEN; ELSIF (coin_s <= "10") THEN next_state <= GOTFIV; END IF; WHEN GOTTEN => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s ="00") THEN next_state <= GOTTEN; ELSIF (coin_s="01") THEN next_state <= GOTFIV; ELSIF (coin_s="10") THEN next_state <= GOTTWEN; END IF; WHEN GOTFIF => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIF; ELSIF (coin_s ="01") THEN next_state <= GOTTWEN; ELSIF (coin_s = "10") THEN next_state <= GOTTWEN; END IF; WHEN GOTTWEN => next_state <= CAR_PAID; WHEN CAR_PAID => IF (car_s = '0') THEN next_state <= NO_CAR; ELSE next_state<= CAR_PAID; END IF; WHEN CHEATED => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= CHEATED; END IF; END CASE; END PROCESS;-----End of Process 1 -------PROCESS 2 for STATE REGISTER CLOCKING-------- PROCESS(Clock,RE) BEGIN IF RE = '1' THEN present_state <= GOTZERO; ----When the clock changes from low to high,the state of the system ----stored in next_state becomes the present state----- ELSIF Clock'EVENT AND Clock ='1' THEN present_state <= next_state; END IF; END PROCESS;-----End of Process 2------- --------------------------------------------------------- -----Conditional signal assignment statements---------- r_light <= '0' WHEN present_state = CAR_PAID ELSE '1'; g_light <= '1' WHEN present_state = CAR_PAID ELSE '0'; alarm <= '1' WHEN present_state = CHEATED ELSE '0'; END Behav;

3808


what is an unbalance in acircuit? in a three phase 3wire circuit how an unbalance will come? in a three phase four wire system how an un balance is coming?

564


Whether setting up of diary plants comes under CMA under Farm Sector or Non Farm Sector

478


How to delete software errors? What is that?

706


What is depreciation factor?

797






Could the power factor on electrical system can affect the registration of the kwhr meter or the CT/PT? 

676


A 100KVA SINGLE PHASE TRANSFORMER 10000/200V,50HZ REQUIRES 300V AT HV SIDE TO CIRCULATE FULL LOAD CURRENT WITH LV SHORT CIRCUITED.THE INTAKE IS 1000W.THE % OF REGULATION ON FULL LOAD AT 0.8 PF LAGGING WILL BE HOW MUCH AND THE SECONDARY TERMINAL VOLTAGE ON 0.8 PF LEADING WILL BE

1027


explain the methodology of Data Warehousing?(Polaries)

1034


how the efficency of a coupling is calculated?

1320


thermal engineering

6501


what r the main attributes of test automation?

710


Why is better to have a minimum ceiling voltage of 250% than 160%?

589


Objectives and Correlating Incentives Describe a time when you have set objectives and correlating incentives for a member of your team What were you trying to achieve in doing this, what were the objectives? How did you choose the incentives?

628


which is the best institute for PLC,SCADA,DCS in hyderabad

995


How many RRI we can use in One BTS?

827






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