What?s the difference between Testing & Verification?
- 6 Answers
- 28008 Views
- Infosys, I also Faced
- E-Mail Answers
Answer Posted / john
Testing is the process of identifying defects in a product.
Verification is the process of ensuring that the product
complies with its specification. Validation is the process
of ensuring that the product meets the users' needs.
Although linked, these are obviously separate. A product may
be defect free but not what was specified or needed; it may
have defects and be not as specified, but may still meet
user need; it may meet specification, but have defects and
not meet the users' need (probably the most common outcome
of software projects!).
| Is This Answer Correct ? | 30 Yes | 2 No |
Post New Answer View All Answers
Explain the operation of a 6T-SRAM cell?
what is the use of defpararm?
6-T XOR gate?
Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
what is SCR (Silicon Controlled Rectifier)?
Give the cross-sectional diagram of the cmos.
Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
What is the difference between nmos and pmos technologies?
Explain what is the use of defpararm?
For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
What is Body Effect?
Explain how binary number can give a signal or convert into a digital signal?
Mention what are the two types of procedural blocks in Verilog?
Differences between Array and Booth Multipliers?
