Implement D flip-flop with a couple of latches? Write a VHDL
Code for a D flip-flop?
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Answer Posted / hps
ibrary IEEE;
use IEEE.STD_LOGIC_1164.all;
entity gh_DFF is
port(
D : in STD_LOGIC;
CLK : in STD_LOGIC;
rst : in STD_LOGIC;
Q : out STD_LOGIC
);
end gh_DFF;
architecture a of gh_DFF is
begin
process(CLK,rst)
begin
if (rst = '1') then
Q <= '0';
elsif (rising_edge(CLK)) then
Q <= D; // The latch should_not be included
// ie:- instead of D ; D should used
end if;
end process;
end a;
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