Answer Posted / arpit raj
Buses are divided into three subassemblies:
The address bus transports memory addresses which the
processor wants to access in order to read or write data. It
is a unidirectional bus.
The data bus transfers instructions coming from or going to
the processor. It is a bidirectional bus.
The control bus transports orders and synchonisation signals
coming from the control unit and travelling to all other
hardware components. It is a bidirectional bus, as it also
transmits response signals from the hardware.
There are primary buses which are of two types:
There are generally two buses within a computer:
the internal bus (front-side bus, or FSB for short). The
internal bus allows the processor to communicate with the
system's central memory (the RAM).
the expansion bus (input/output bus) allows various
motherboard components (USB, serial, and parallel ports,
cards inserted in PCI connectors, hard drives, CD-ROM and
CD-RW drives, etc.) to communicate with one another.
However, it is mainly used to add new devices using what are
called expansion slots connected to the input/outpur bus.
| Is This Answer Correct ? | 20 Yes | 0 No |
Post New Answer View All Answers
Explain the three regions of operation of a mosfet.
What are the different design techniques required to create a layout for digital circuits?
What types of high speed CMOS circuits have you designed?
What is the difference between the mealy and moore state machine?
Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
Explain CMOS Inverter transfer characteristics?
Give various factors on which threshold voltage depends.
Explain how MOSFET works?
Draw the Layout of an Inverter?
How can you model a SRAM at RTL Level?
Explain how logical gates are controlled by Boolean logic?
Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
Differences between Array and Booth Multipliers?
What are the different measures that are required to achieve the design for better yield?
Explain why present VLSI circuits use MOSFETs instead of BJTs?
