Factors affecting Power Consumption on a chip?
Answer Posted / subu
1) Number of state Transition.
2) Ideal clock input (instead we can give clock gating)
Is This Answer Correct ? | 5 Yes | 2 No |
Post New Answer View All Answers
Explain what is the use of defpararm?
Explain how logical gates are controlled by Boolean logic?
What are the different measures that are required to achieve the design for better yield?
what are three regions of operation of MOSFET and how are they used?
Explain the Charge Sharing problem while sampling data from a Bus?
Draw a 6-T SRAM Cell and explain the Read and Write operations
Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
Explain the working of Insights of a pass gate ?
Explain sizing of the inverter?
Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
Explain what is the depletion region?
If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?
Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
If the current through the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?