Which gate is normally preferred while implementing circuits
using CMOS logic, NAND or NOR? Why?
- 13 Answers
- 33499 Views
- Intel, I also Faced
- E-Mail Answers
Answer Posted / sarang
NAND is a better gate for design than NOR because at the
transistor level the mobility of electrons of NAND is
normally three times that of holes compared to NOR and thus
the NAND is a faster gate. The gate-leakage in NAND
structures is much lower. If you consider t_phl and t_plh
delays you will find that it is more symmetric in case of
NAND (the delay profile), but for NOR, one delay is much
higher than the other(obviously t_plh is higher since the
higher resistance PMOSs are in series connection which
again increases the resistance).
| Is This Answer Correct ? | 18 Yes | 6 No |
Post New Answer View All Answers
Explain how logical gates are controlled by Boolean logic?
Explain how binary number can give a signal or convert into a digital signal?
What happens if we delay the enabling of Clock signal?
Explain why is the number of gate inputs to cmos gates usually limited to four?
What is the purpose of having depletion mode device?
what are three regions of operation of MOSFET and how are they used?
Explain sizing of the inverter?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.
Explain what is Verilog?
Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
What does the above code synthesize to?
what is the use of defpararm?
What types of high speed CMOS circuits have you designed?
What is the difference between cmos and bipolar technologies?
What are the different design constraints occur in the synthesis phase?
