Interested to Buy Any Domain ? << Click Here >> for more details...
Which gate is normally preferred while implementing circuits
using CMOS logic, NAND or NOR? Why?
- 13 Answers
- 37512 Views
- Intel, I also Faced
- E-Mail Answers
Answer Posted / sarang
NAND is a better gate for design than NOR because at the
transistor level the mobility of electrons of NAND is
normally three times that of holes compared to NOR and thus
the NAND is a faster gate. The gate-leakage in NAND
structures is much lower. If you consider t_phl and t_plh
delays you will find that it is more symmetric in case of
NAND (the delay profile), but for NOR, one delay is much
higher than the other(obviously t_plh is higher since the
higher resistance PMOSs are in series connection which
again increases the resistance).
| Is This Answer Correct ? | 18 Yes | 6 No |
Post New Answer View All Answers
What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
Are you familiar with the term MESI?
What is the purpose of having depletion mode device?
Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
How does a Bandgap Voltage reference work?
What are the ways to Optimize the Performance of a Difference Amplifier?
What is the difference between cmos and bipolar technologies?
What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
Explain how MOSFET works?
What are the Advantages and disadvantages of Mealy and Moore?
What are the different design constraints occur in the synthesis phase?
Basic Stuff related to Perl?
Are you familiar with the term snooping?
What are the changes that are provided to meet design power targets?
