Answer Posted / venkatesh

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

1051

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Explain why present VLSI circuits use MOSFETs instead of BJTs?

645

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What happens if we delay the enabling of Clock signal?

1798

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In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

689

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Write a VLSI program that implements a toll booth controller?

3493

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For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?

732

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Explain CMOS Inverter transfer characteristics?

3440

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Explain Cross section of an NMOS transistor?

564

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Working of a 2-stage OPAMP?

2600

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What was your role in the silicon evaluation or product ramp? What tools did you use?

1854

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What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

2348

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Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

671

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What are the different ways in which antenna violation can be prevented?

659

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Implement F= not (AB+CD) using CMOS gates?

3517

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For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

707

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