Explain about stuck at fault models, scan design, BIST and
IDDQ testing?
- 3 Answers
- 12078 Views
- Intel, I also Faced
- E-Mail Answers
Answer Posted / seetharamukg
IDDQ testing is used for testing the library cells. Meaning
if any faults are there in our design we are going for DFT.
If any faults are there in the library itself we are doing
IDDQ testing.
| Is This Answer Correct ? | 3 Yes | 9 No |
Post New Answer View All Answers
what is the difference between the TTL chips and CMOS chips?
Explain how Verilog is different to normal programming language?
How do you size NMOS and PMOS transistors to increase the threshold voltage?
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
Explain the operation of a 6T-SRAM cell?
If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?
what is verilog?
Give the cross-sectional diagram of the cmos.
Explain depletion region.
For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?
What is the ideal input and output resistance of a current source?
What types of CMOS memories have you designed? What were their size? Speed?
What was your role in the silicon evaluation or product ramp? What tools did you use?
How logical gates are controlled by boolean logic?
