Answer Posted / ahamed.s

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What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

2362

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Explain what is the use of defpararm?

665

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

1060

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Explain how MOSFET works?

2810

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Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

616

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Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

678

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How binary number can give a signal or convert into a digital signal?

694

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6-T XOR gate?

3799

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What is the difference between the mealy and moore state machine?

599

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Explain what is scr (silicon controlled rectifier)?

625

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Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)

904

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In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

3604

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Explain Cross section of a PMOS transistor?

751

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For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?

743

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In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?

591

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