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Infosys Interview Questions
Questions Answers Views Company eMail

Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.

 692

Draw the stick diagram of a NOR gate. Optimize it

 752

Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

 716

Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

 671

Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.

 664

Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

 685

Draw a 6-T SRAM Cell and explain the Read and Write operations

 795

Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

 1063

You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

 951

What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

 762

Draw a CMOS Inverter. Explain its transfer characteristics

 667

How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?

 734

For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

 706

For CMOS logic, give the various techniques you know to minimize power consumption

 850

What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus

 780

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Infosys Interview Questions


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