Interested to Buy Any Domain ? << Click Here >> for more details...
Give the various techniques you know to minimize power
consumption?
- 5 Answers
- 13262 Views
- I also Faced
- E-Mail Answers
Answer Posted / jaya suriya.i
1.reduce the vdd.its
2.using short channel devices(its very complicated).
3.reduce the load capacitance of cmos..
| Is This Answer Correct ? | 0 Yes | 0 No |
Post New Answer View All Answers
What is the purpose of having depletion mode device?
Draw a 6-T SRAM Cell and explain the Read and Write operations
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?
Implement a 2 I/P and gate using Tran gates?
what is a sequential circuit?
Explain the Various steps in Synthesis?
What was your role in the silicon evaluation or product ramp? What tools did you use?
what is multiplexer?
What types of CMOS memories have you designed? What were their size? Speed?
Explain Basic Stuff related to Perl?
What are the different ways in which antenna violation can be prevented?
What transistor level design tools are you proficient with? What types of designs were they used on?
What is the difference between the mealy and moore state machine?
What is the function of tie-high and tie-low cells?
