Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...

Give the various techniques you know to minimize power
consumption?

Answer Posted / jaya suriya.i

1.reduce the vdd.its
2.using short channel devices(its very complicated).
3.reduce the load capacitance of cmos..

Is This Answer Correct ?    0 Yes 0 No



Post New Answer       View All Answers


Please Help Members By Posting Answers For Below Questions

Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers

1059


Explain sizing of the inverter?

4369


What are the different design techniques required to create a layout for digital circuits?

995


What is the function of tie-high and tie-low cells?

1031


Explain various adders and difference between them?

1153


Draw the stick diagram of a NOR gate. Optimize it

1225


Explain how Verilog is different to normal programming language?

1180


Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3821


In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

1127


Explain the Charge Sharing problem while sampling data from a Bus?

4658


Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram

1409


How do you size NMOS and PMOS transistors to increase the threshold voltage?

2967


What types of CMOS memories have you designed? What were their size? Speed?

4605


What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

2835


What is the purpose of having depletion mode device?

988