Answer Posted / jaya suriya.i

1.reduce the vdd.its
2.using short channel devices(its very complicated).
3.reduce the load capacitance of cmos..

Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

1581

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In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

4099

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How does Vbe and Ic change with temperature?

3502

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Explain Cross section of a PMOS transistor?

1212

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Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

2313

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Explain the Working of a 2-stage OPAMP?

1182

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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.

1097

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What are the main issues associated with multiprocessor caches and how might you solve them?

2207

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Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

1439

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Explain CMOS Inverter transfer characteristics?

3899

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What does it mean “the channel is pinched off”?

1343

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If not into production, how far did you follow the design and why did not you see it into production?

2079

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What transistor level design tools are you proficient with? What types of designs were they used on?

5055

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What are the steps required to solve setup and hold violations in vlsi?

1067

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Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

1058

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