Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...

In what cases do you need to double clock a signal before
presenting it to a synchronous state machine?

Answer Posted / prashant patil

if the input signal is asynchronous with the clock (state
machine clock), then you need to double clock the same
signal to synchronize with the state machine clock.

Is This Answer Correct ?    21 Yes 7 No



Post New Answer       View All Answers


Please Help Members By Posting Answers For Below Questions

What is the purpose of having depletion mode device?

987


Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.

2785


Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

1397


What are the different design constraints occur in the synthesis phase?

1062


If not into production, how far did you follow the design and why did not you see it into production?

2049


Cross section of a PMOS transistor?

4720


What is the function of tie-high and tie-low cells?

1030


Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.

1056


What is Body Effect?

2463


What is the main function of metastability in vsdl?

1004


You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

1504


Draw the Layout of an Inverter?

2442


Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

1586


What is the difference between the mealy and moore state machine?

1035


What happens if we delay the enabling of Clock signal?

2299