Answer Posted / amit malik

PS I/P NS O/P
S0 0 S0 0
S0 1 S1 0
S1 0 S0 0
S1 1 S2 0
S2 0 S3 0
S2 1 S2 0
S3 0 S0 0
S3 1 S1 1

Explain how MOSFET works?

3226

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Explain what is slack?

1053

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Differences between Array and Booth Multipliers?

4061

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Explain why is the number of gate inputs to cmos gates usually limited to four?

1489

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What is Noise Margin? Explain the procedure to determine Noise Margin?

2442

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

1581

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Insights of a 4bit adder/Sub Circuit?

3343

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What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

3247

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What happens if we use an Inverter instead of the Differential Sense Amplifier?

3297

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What happens if we use an Inverter instead of the Differential Sense Amplifier?

2984

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What transistor level design tools are you proficient with? What types of designs were they used on?

3424

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Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.

2827

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What was your role in the silicon evaluation or product ramp? What tools did you use?

2294

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3853

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For CMOS logic, give the various techniques you know to minimize power consumption

1387

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