Answer Posted / chaitanya
SETUP time : Minimum time the data should be stable before
the arrival of clock edge
HOLD time : Minum time data shuold be stable after the
arrival of clock edge.
| Is This Answer Correct ? | 21 Yes | 0 No |
Post New Answer View All Answers
Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
For CMOS logic, give the various techniques you know to minimize power consumption
What are the different design techniques required to create a layout for digital circuits?
How can you construct both PMOS and NMOS on a single substrate?
What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
What are the main issues associated with multiprocessor caches and how might you solve them?
What is the ideal input and output resistance of a current source?
Describe the various effects of scaling?
Implement a 2 I/P and gate using Tran gates?
How do you size NMOS and PMOS transistors to increase the threshold voltage?
what are three regions of operation of MOSFET and how are they used?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
In Verilog code what does “timescale 1 ns/ 1 ps” signifies?
What are the various regions of operation of mosfet? How are those regions used?
What happens if we use an Inverter instead of the Differential Sense Amplifier?