Answer Posted / madhu
Latch-up is a condition in which the parasitic components
give rise to the Establishment of low resistance conducting
path between VDD and VSS with Disastrous results.
| Is This Answer Correct ? | 41 Yes | 4 No |
Post New Answer View All Answers
Mention what are the different gates where Boolean logic are applicable?
Draw a 6-T SRAM Cell and explain the Read and Write operations
How to improve these parameters? (Cascode topology, use long channel transistors)
What is the difference between nmos and pmos technologies?
Insights of a 4bit adder/Sub Circuit?
Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
Explain what is slack?
For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
why is the number of gate inputs to CMOS gates usually limited to four?
what is the use of defpararm?
If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?
Implement a function with both ratioes and domino logic and merits and demerits of each logic?
What are the main issues associated with multiprocessor caches and how might you solve them?
If the current through the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?
what is the difference between the TTL chips and CMOS chips?