Answer Posted / Alakh Jain
A D-Latch using Transmission Gates consists of two latches in series, with one enabled at a time. It has four inputs: D (data input), CLK (clock input), Enable (EN), and Q (output).
In the set mode (when EN is high):
- The transmission gate between latch 1 and latch 2 is closed, allowing data from latch 1 to pass through to latch 2. The clock signal does not affect the data stored in the latches.
In the sample mode (when EN is low):
- The transmission gate between latch 1 and latch 2 opens, allowing data from the clock enable input to be stored in both latches. The clock input determines which bit of data will be sampled.
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