Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.)
Inputs AND OUTPUTS:
entity Lab4b is
Port ( Clr, Clk, D : in STD_LOGIC;
Q : out STD_LOGIC);
end Lab4b;
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Answer Posted / Shruti Goswami
Here's a simple VHDL code for a D-Latch with Clear input:nn```vhdlnentity Lab4b isn Port ( Clr, Clk, D : in STD_LOGIC;n Q : out STD_LOGICn );nend Lab4b;nnarchitecture Behavioral of Lab4b isnbeginn process(Clk, Clr)n beginn if rising_edge(Clk) thenn if Clr = '1' thenn Q <= '0';n elsen Q <= D;n end if;n end if;n end process;nend Behavioral;n```
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