Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...

Differences between DRAM and SRAM?

Answer Posted / mohammed juned

Static Ram are fast, but they come at high cost because their several transistoras. Less expensive ram can be implement if simpler cells are used. However, such cell do not retain their state indefinitely; hence, they are called dynamic RAM

Is This Answer Correct ?    1 Yes 0 No



Post New Answer       View All Answers


Please Help Members By Posting Answers For Below Questions

Explain what is the depletion region?

1031


what is multiplexer?

1100


What is Noise Margin? Explain the procedure to determine Noise Margin?

2415


Draw the stick diagram of a NOR gate. Optimize it

1227


What are the different classification of the timing control?

1052


Are you familiar with the term snooping?

3433


What are the different measures that are required to achieve the design for better yield?

1167


What are the different design techniques required to create a layout for digital circuits?

997


For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

1394


What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

3210


Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3822


What is the main function of metastability in vsdl?

1008


What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

2836


what is the use of defpararm?

1102


Explain the Charge Sharing problem while sampling data from a Bus?

4659