Interested to Buy Any Domain ? << Click Here >> for more details...
Answer Posted / teja
LVS mean layout versus schematic.What it actually mean is, it compares between the layout.xp file which was been created from layout and the netlist of schematic.If any mismatch in the connections it will show errors.Now what is layout.xp is, first layout creates gds file through that gds file layout.xp file will be created(we can say this as netlist of layout)and comparision between them takes place while we run lvs..
DRC mean it is just design rules check.It checks complete layout if there are any violations in the layout with respect to the technology files (like spacings enclosers,widths,areas,endcaps ete etc) it will generate errors..
| Is This Answer Correct ? | 11 Yes | 0 No |
Post New Answer View All Answers
Explain what is Verilog?
Explain the operation of a 6T-SRAM cell?
Mention what are the different gates where Boolean logic are applicable?
What is the difference between nmos and pmos technologies?
If the current through the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.
Explain how MOSFET works?
why is the number of gate inputs to CMOS gates usually limited to four?
Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
Are you familiar with the term snooping?
What products have you designed which have entered high volume production?
What is threshold voltage?
In Verilog code what does “timescale 1 ns/ 1 ps” signifies?
Write a program to explain the comparator?
What was your role in the silicon evaluation/product ramp? What tools did you use?
