Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...

What is LVS, DRC?

Answer Posted / teja

LVS mean layout versus schematic.What it actually mean is, it compares between the layout.xp file which was been created from layout and the netlist of schematic.If any mismatch in the connections it will show errors.Now what is layout.xp is, first layout creates gds file through that gds file layout.xp file will be created(we can say this as netlist of layout)and comparision between them takes place while we run lvs..

DRC mean it is just design rules check.It checks complete layout if there are any violations in the layout with respect to the technology files (like spacings enclosers,widths,areas,endcaps ete etc) it will generate errors..

Is This Answer Correct ?    11 Yes 0 No



Post New Answer       View All Answers


Please Help Members By Posting Answers For Below Questions

What are the Advantages and disadvantages of Mealy and Moore?

1195


Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?

3332


How do you size NMOS and PMOS transistors to increase the threshold voltage?

2968


Explain the working of 4-bit Up/down Counter?

4396


How does Vbe and Ic change with temperature?

3466


Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3823


For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?

1196


In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

1129


Explain the operation of a 6T-SRAM cell?

4472


What products have you designed which have entered high volume production?

2393


For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

1394


what is SCR (Silicon Controlled Rectifier)?

1002


For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

1228


What are the various regions of operation of mosfet? How are those regions used?

1078


Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.

1059